This invention relates generally to packaged semiconductor chip devices which have mirrored external terminals. The present invention further relates to memory modules and other devices which include such mirrored packaged semiconductor chip devices, test devices for testing mirrored packaged semiconductor devices, and methods of testing such mirrored packaged semiconductor devices.
Semiconductor chip devices, or so-called xe2x80x9cdice,xe2x80x9d are well known in the art. Such devices may include combinations of any of a large number of active semiconductor components, such as diodes and/or transistors, with various passive components, such as capacitors and/or resistors, all residing on a wafer, e.g., made of silicon or gallium arsenide, or other materials. Many different types of semiconductor chip devices are made using different combinations of materials and known manufacturing procedures. Typically, a starting substrate, such as a thin wafer of silicon, is subjected to various combinations of steps such as material deposition, oxidizing, nitridizing, ion implantation, diffusion, doping, masking, etching and others. In these treatments, the specific materials and sequence of steps are selected so as to produce semiconductor components having specific desired functions. The semiconductor components are arranged so as to provide a semiconductor chip device having specified functions, for example, as a memory, such as an SRAM or a DRAM, as is well known in the art.
Each semiconductor chip device has a plurality of die bond pads positioned on or in the chip device which are connected to external terminals or xe2x80x9cpinsxe2x80x9d of an integrated circuit package. It is through these terminals or pins of a package that the semiconductor chip device, and thus the semiconductor components in the chip, electrically communicate with the outside world.
Each different terminal or pin connects to circuitry in or on the semiconductor chip device which provides a particular function. For example, a memory chip may have input-output lines (such as data lines), input only lines (such as clock lines or address lines), ground lines, and one or more power lines. It is through these individual connections that the semiconductor chip device derives all necessary power, ground, input-output and input only signals. There are a variety of known semiconductor chip devices and associated packages which include a large number of such terminals, and as chips become even more dense and feature rich, the number of external terminals required continues to grow.
A common example of a commercial article which includes packaged memory chip devices is a memory module. A memory module typically includes several packaged memory chip devices mounted on a module board, e.g., a printed circuit board. In such a module, each packaged memory chip device has a plurality of external terminals electrically connected to a respective module board electrical connector. The module board provides physical support for the packaged semiconductor device, and electrically connects it to other external circuitry via the module board electrical connectors.
Examples include single in-line memory modules (SIMM""s), which are multi-chip memory modules having multiples of the same basic die. In a SIMM, the semiconductor memory chips are typically aligned in a row and interconnected on a printed circuit board to, in effect, create a single device with the memory capacity of the combined memory chips. The wiring pattern of the printed circuit board connects packaged semiconductor devices to module terminals, e.g., along one edge of the printed circuit board. The module terminals may be configured for attachment to an edge-type connector, such as a SIMM socket, as is known in the art.
Another known memory module is a dual in-line memory module (DIMM). On a DIMM, memory chips are mounted on both surfaces of a circuit board. To simplify the mounting and wiring of a memory module having packaged memory chips on both sides of the module board, mirrored packaged memory chips have been developed, so that a packaged memory chip can be mounted on one side of the board and a mirror image of the packaged memory chip can be mounted to the same module board pads on the other side of the board. Such pairs of packaged memory chips are referred to as xe2x80x9cmirror pairsxe2x80x9d or xe2x80x9cmirror imagesxe2x80x9d, i.e., the external terminals of each mirror pair are positioned opposite one another on opposite surfaces of the module and connect to the same board bonding site. The expressions xe2x80x9cmirror pairxe2x80x9d and xe2x80x9cmirror imagexe2x80x9d are used herein to refer to pairs of packaged memory chips having external terminal arrangements which are asymmetrical. The external terminal arrangements of members of a mirror pair, e.g., memory chips, which are mirror images of each other, are necessarily non-identical. The expression xe2x80x9cmirror pairxe2x80x9d is used herein to refer to the packaged memory chips whether or not one or both of them are attached to a module board (i.e., on opposite sides of the module board). Also, one member of a mirror pair is referred to herein as a xe2x80x9cmirror pairxe2x80x9d of the other member and/or a xe2x80x9cmirror imagexe2x80x9d of the other member.
In the manufacture of any of the many articles which include one or more packaged semiconductor chip devices, e.g., memory devices, it has been found that it is inefficient and wasteful to construct the entire article, or a substantial part of it, and later discover that one or more of the packaged semiconductor chip devices is defective or damaged. Therefore, packaged semiconductor chip devices are usually tested prior to mounting them on a circuit board or module. For example, such testing includes testing the die devices for speed and for errors which may occur after fabrication and after burn-in. Burn-in testing is typically conducted at elevated potentials and for a prolonged period of time (e.g., 24 hours), at varying and reduced and elevated surrounding temperatures (such as xe2x88x9215xc2x0 C. to 125xc2x0 C.). Such burn-in testing is designed to accelerate failure mechanisms such that die devices which have the potential to prematurely fail during normal operation can be identified and eliminated.
Test devices typically include electrical contact elements (or test head pads), as well as structure, such as a socket or other connection, which acts alone or in combination with a carrier to hold the article being tested at a specific location and in a specific orientation. Since the article is constructed so as to conform to specific dimensional specifications, the electrical contact elements in the test devices reliably make electrical connection with the respective die bondpads on the article, or they make connection with respective elements, e.g., external package terminals, which are in electrical connection with the internal semiconductor device circuitry.
The testing of the packaged semiconductor chip device typically comprises a first series of electrical tests, burn-in of the chip, and a second series of electrical tests. The electrical tests may comprise, for instance, a set of tests to verify that the semiconductor die meets certain speed specifications, a set of tests to verify that the chip device meets specific voltage, capacitance and current specifications, and a set of tests to verify that the chip properly performs the function or functions for which it was designed and over a desired lifespan.
Test devices, including a burn-in oven and test equipment, are relatively expensive. In addition, test devices require electrical circuitry which is specific to the external terminal arrangement on the packaged device being tested. For example, with the test device described above, for each type of packaged device (i.e., for each external terminal arrangement), it is necessary to have a specially designed lid and/or a specially designed carrier.
In the case of mirrored packaged memory chips, the two members of a mirror pair have different (i.e., mirror image) external terminal arrangements, which are not identical to one another. It has therefore not been possible to easily test both types of packaged memory chips of a mirrored pair using a single test device. In addition, damage can occur if a chip which is of one type of chip in a mirror pair is in error brought into engagement with a test device adapted for testing the other type of chip in that mirror pair. Since the one type of chip in the mirror pair is a mirror image of the other type of chip in the mirror pair, the electrical contact elements in the test device will be in contact with incorrect external terminals (mismatching). When such mismatching takes place, it is possible to severely damage the memory chip and/or the test device. As a result, in order to test the two types of chips used in a mirrored memory module, it has been necessary to incur the cost of two types of testing hardware, to provide space for the two types of hardware, to expend the time required to change a component in a test device, and/or to separately test the members of a mirror pair.
Attempts have been made to simplify the testing of IC chips or modules containing them. U.S. Pat. No. 5,667,077 discloses an apparatus for testing and handling multi-chip modules (MCM""s). The patent discloses a double-sided MCM in position for testing by a test device. The test device makes electrical contact with the edge connector traces of the MCM using upper and lower contactor pins. The upper and lower contactor pins are mounted into upper and lower contactor assemblies which are programmed to raise and lower, as necessary, to make contact with the MCM when it is in position and ready for testing.
U.S. Pat. No. 5,502,621 discloses that in the past, circuit boards incorporating more than one IC of the same type have been simplified and that problems associated with crossover and crosstalk have been minimized by using pairs of integrated circuits designed with two identical but reversed pin assignments. This patent discloses circuit boards having at least one IC mounted on each side of a two sided board which use one or more ICs having pin assignments arranged as a mirror image of each other along a centerline through the IC package in the X or Y axis. The patent discloses that mounting one or more ICs having the same set of mirror image pin assignments on each side of a circuit board and rotated 180 degrees in relationship to each other will ensure that the pin assignments of the same type (such as ground and power) will be directly opposite each other and separated by the circuit board. Various ground, power, data, strobe, clock and address leads around the chip package have pin assignments which are positioned as a mirror image of each other. These pin assignment requirements thus require that the pin assignment arrangement be symmetrical about the mirror axis. In addition, these pin assignment requirements make it necessary that each pin assignment be duplicated in the packaged device.
U.S. Pat. No. 5,270,964 discloses a SIMM having a connector including contact regions, each of which consist of a large number of closely spaced contact pads on one side of the SIMM and a mirror image yet electrically distinct set of contact pads on the other side of the SIMM. All power and ground leads are symmetrically arranged within the connector, the power and ground leads alternating every sixteen pins. According to the patent, if the SIMM is inadvertently inserted in a reversed position into a memory module socket, the symmetrical power ground leads prevent the SIMM from being reverse-powered, and likely destroyed.
Significant capital savings and process simplification would be obtained by providing a packaged semiconductor device which can be tested using the same test device as is used to test the mirror image packaged semiconductor device. There is furthermore a need for a packaged semiconductor device which eliminates the possibility of damage to the packaged semiconductor device and/or the test device resulting from mismatching caused by engaging the incorrect member of a mirror pair with a test device designed for the other members of the mirror pair.
The present invention provides packaged semiconductor devices each having one or more semiconductor components and a plurality of external terminals. The external terminals are each of a particular function type, such function types including (1) input-output, (2) input only, (3) power and (4) ground. In some implementations there may also be various levels and their classifications of the power terminals. For example, in one more specific memory device aspect the plurality of external terminals are classified by function as (1) input-output, (2) input-only, (3) power for CMOS input and output pins, (4) power for the RDRAM core and interface logic or for the RDRAM analog circuitry, (5) power for threshold reference voltage for RSL signals and (6) ground. The external terminals of packaged semiconductor device according to the present invention are arranged such that the function type of each external terminal of the packaged semiconductor device is the same as that in a corresponding location of a mirror image of the packaged semiconductor device. In other words, for the purpose of explanation, each external terminal of the packaged semiconductor device is classified according to whether it carries input and output (i.e., an input-output terminal), input only (i.e., an input terminal), power and ground. As noted, the power may be further classified and in one specific aspect, each external terminal is classified according to whether it carries input and output, input only, power for CMOS input and output pins (i.e., a power for CMOS input and output pins terminal), power for the RDRAM core and interface logic or for the RDRAM analog circuitry (a power for the RDRAM core and interface logic or for the RDRAM analog circuitry terminal), power for threshold reference voltage for RSL signals and ground pins (i.e, a power for threshold reference voltage for RSL signals and ground pins terminal) or ground (i.e., a ground terminal). This classification is referred to herein as the xe2x80x9cfunction assignmentxe2x80x9d of a terminal, and the arrangement of the terminals of a packaged semiconductor device is referred to herein as the xe2x80x9cfunction assignment arrangementxe2x80x9d of the device. Thus, the function assignment arrangement of a packaged semiconductor device according to the present invention is identical to the function assignment arrangement of a mirror image of that packaged semiconductor device.
There are further provided test devices having pads arranged for engaging the external terminals of the packaged semiconductor device being tested, with the test device pads being electrically connected to circuitry for delivering and receiving input-output, input, power and ground, or for the more specific aspect of the invention, input-output, input, power for CMOS input and output pins, power for the RDRAM core and interface logic or for the RDRAM analog circuitry, power for threshold reference voltage for RSL, and ground signals. As with the external terminals of packaged semiconductor devices, the test device pads are each classified, for purposes of explanation, according to their particular function. In accordance with the present invention, the test device pads have a function assignment arrangement which matches the function assignment arrangement of the packaged semiconductor device being tested.
For each semiconductor chip device according to the present invention, and its mirror pair, a single test device can be used to test both members of the mirror pair.
Depending upon which of the two members of the mirror pair is being tested (this information can be input by the user or sensed from information on the packaged device itself, software applies the corresponding pad assignments to the pads on the test device. In other words, when one member of a mirror pair is being tested, based on information as to which member of the mirror pair is being tested, software causes signals to be re-routed and/or altered, as necessary, internally in order to properly complete the test. Software can accommodate both members of a mirror pair, because it can modify the pattern of signals sent from the test device to account for the substitution of one terminal of a particular function assignment for another terminal of the same function assignment (e.g., one input-output terminal may be in a particular location on one member of a mirror pair, and a different input-output terminal may be in that location in the other member of the mirror pair). However, software cannot easily account for substitution of a terminal of one function type for a terminal of another function type. Although the terminal arrangements of both members of mirror pairs according to the present invention are asymmetrical, the function assignment arrangements of both members of such mirror pairs are symmetrical, so that the external terminal in any position of one member of a mirror pair is the same as the external terminal located in the corresponding position of the other member of the mirror pair.
Also, in the event that a packaged device is being tested and the function assignment arrangement of the test device is incorrectly set for the mirror image of the packaged device, there is no possibility for damage to the device or the test device. Contrary to prior art devices, such damage is avoided because all pins of both members of a mirror pair according to the present invention are connected to pins of the same function type in the test device.
The present invention also relates to mirrored memory modules which include one or more semiconductor chip devices according to the present invention, in particular, mirror pairs in which the respective members of each mirror pair are positioned on opposite sides of a module board. The present invention further relates to process devices, e.g., computers, workstations, etc., which include such mirrored memory modules having the terminal arrangement of the invention.
In addition, the present invention relates to methods of testing semiconductor chip devices using test devices capable of accepting either member of a mirror pair.